Method of making conductive paths through a lamina in a semiconductor device
US4378383A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 1981 |
| Grant date | Mar 29, 1983 |
| Priority date | — |
| Expiry date | Oct 19, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
On the layer 12 a mask 3 corresponding to the desired pattern of holes 15 is provided with via openings 14 having overhanging walls. The layer 12 is selectively etched with a method where the etching attack takes place vertically to the layer surface, and wherein the mask 3 is thinned simultaneously, so that holes 15 are obtained having a cross-section increasing toward the mask 3. If subsequently material 16 for filling the holes 15 is applied in a blanket deposition these holes are completely filled when the material 16 has the same thickness as the layer 12 although the openings over the holes are decreasing with increasing thickness of the material 16. The layer 12 consists preferably of an insulation material, the mask 3 of positive photoresist, and the material 16 of a metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.