Emitter function logic latch and counter circuits
US4378505A · kind A · utility
5Cited by
5References
39Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1980 |
| Grant date | Mar 29, 1983 |
| Priority date | — |
| Expiry date | Sep 29, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/2885
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An EFL D-type latch employing an EFL storage cell (17) controlled by a two-level tree of differential transistor pairs (12, 14 and 32, 34). Also described are counter cells, up counters, down counters and up/down counters, including binary, hexadecimal and BCD types, which can be formed from master/slave combinations of D-type and D-type latches. Examples of specific three-level and four-level EFL realizations of the counter cells are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.