EFL Logic arrays
US4378508A · kind A · utility
1Cited by
5References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1980 |
| Grant date | Mar 29, 1983 |
| Priority date | — |
| Expiry date | Sep 29, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0863
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic gate is formed as a full 3-EFL circuit including a full two-level ECL current switch tree and an EFL stage made up of input and output multiemitter transistors. By appropriate connections, the logic gate may be used for a variety of circuits including a 4:1 multiplexer and a comparator of two three-digit binary numbers. The logic gate advantageously is formed in a silicon chip which includes an array of cells each consisting essentially of nine single-emitter transistors, two four-emitter transistors and a number, advantageously nine, of resistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.