Static RAM memory cell
US4380055A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 24, 1980 |
| Grant date | Apr 12, 1983 |
| Priority date | — |
| Expiry date | Dec 24, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell (10) for storing data having a data line (12) and a bit enable line (16) for receiving control signals is provided. First and second signal lines (24, 26) receive control signals. A first transistor (14) is interconnected to the data line (12) and to the bit enable line (16). A second transistor (20) is connected to the first transistor (14) and to the first control line (24). A third transistor (22) is connected to the first transistor (14) and to the second control line (26). A first inverter (30) is interconnected to the second transistor (20) to form a first node (34) and to the third transistor (22) to form a second node (36). A second inverter (32) is interconnected between the first node (34) and the second node (36).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.