Two stage etching process for through the substrate contacts
US4381341A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1982 |
| Grant date | Apr 26, 1983 |
| Priority date | — |
| Expiry date | Feb 1, 2002 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Electrical interconnection paths or vias are provided through relatively thick type III/V semiconductive substrates, such as gallium arsenide, to permit through the substrate electrical interconnection of planar transistor devices. The vias are etched in a two-step process which ensures that the via lateral dimensions are less than the transistor contacts with which they are aligned. The first step comprises selectively thinning the thick substrate from the back surface over an area which encompasses the transistor array formed in the front surface of the substrate. The second step is to etch the individual vias through this prior thinned substrate at areas aligned with the transistor contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.