System for interrupt arbitration
US4381542A · kind A · utility
24Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1980 |
| Grant date | Apr 26, 1983 |
| Priority date | — |
| Expiry date | Oct 20, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system in which a unit needing to be serviced by a processor first requests an interrupt and, after the interrupt is granted by the processor, requests access to a system bus to transfer interrupt information as it normally would transfer other information. The interrupting unit must wait for other units having higher priority to transfer information, usually memory information over the bus, before it can access the bus to transfer its interrupting information. This permits transfers of information having higher priority to occur before the transfer of the interrupt information is transferred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.