AC Measurement means for use with power control means for eliminating circuit to circuit delay differences
US4383216A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1981 |
| Grant date | May 10, 1983 |
| Priority date | — |
| Expiry date | Jan 29, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/466
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator unde…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.