Data processing system having data entry backspace character apparatus
US4383295A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1979 |
| Grant date | May 10, 1983 |
| Priority date | — |
| Expiry date | Feb 9, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.