Data processing system including internal register addressing arrangements
US4383297A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1980 |
| Grant date | May 10, 1983 |
| Priority date | — |
| Expiry date | Sep 29, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multi-processor system of the type in which each processor is provided with its own unique bus which has an addressing system organized in such a manner that all store locations and peripheral equipments are addressed as part of a comprehensive single addressing system. Each address comprises a module number and an offset address. Each module in the system includes a module number comparator which detects the presence of its module address on a CPU bus and allows the offset address to be active within that module. The invention provides for the incorporation of similar mechanisms within a CPU allowing the CPU to address its own internal registers in an identical manner to its normal bus addressing mode. In addition the offset address includes a "bit portion address" which selects a mask which is used when performing the required internal register operation. The main advantage of such an arrangement is the simplification of the instruction range for the CPU as "normal" instructions may be used to manipulate the internal registers rather than having special purpose instructions dedicated to the manipulating of the registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.