System for reducing access time to plural memory modules using five present-fetch and one prefetch address registers
US4384342A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1980 |
| Grant date | May 17, 1983 |
| Priority date | — |
| Expiry date | Oct 29, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A lookahead (guessahead) prefetching technique is used to reduce the average access time, for accessing memory modules when program addresses are modified into effective addresses for addressing the modules. A first memory address register stores the column address and module designation portions of the current effective address, a second memory address register stores the row address portion of the current effective address, and a third memory address register stores the module designation portion of the prior effective address. Since the same module is frequently accessed many times in succession, the average access time is reduced by starting an access based upon the contents of the second and third memory address registers without waiting until the column address and module designation portions of the current effective address are available for storage in the first memory address register. The access is completed, after the column address and module designation portions of the current effective address are determined, if a comparator which is connected to the first and third memory address registers confirms that the same memory module is being successively accessed. If not, th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.