Method and means for internal error check in a digital memory
US4384353A · kind A · utility
5Cited by
6References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1981 |
| Grant date | May 17, 1983 |
| Priority date | — |
| Expiry date | Feb 19, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor digital memory such as a charge coupled device is provided with error detection capability. Error logic responsive to a group of data on the input bus generates a first error code which is stored in memory along with the group of data. When the data is retrieved from memory similar error logic generates a second error code. The first and second error codes are compared, and if the codes are identical the data is assumed to be correct. If codes differ then the data is discarded or errors therein are identified and corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.