Self-synchronization circuit for a FFSK or MSK demodulator
US4384357A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1981 |
| Grant date | May 17, 1983 |
| Priority date | — |
| Expiry date | Apr 3, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The self-synchronization circuit splits the incoming signal into two circuit paths where the signals are frequency shifted by a frequency signal equal to the carrier frequency so as to provide an in-phase signal in one circuit path and a quadrature signal in the other circuit path. The frequency shifting circuit includes at least a controllable oscillator. The output of a first multiplier which multiplies the in-phase and quadrature signals, is fed to a clock recovery circuit which determines the clock frequency. A second multiplier multiplies the output of the first multiplier with the clock recovery circuit output to provide a signal which controls the controllable oscillator. In addition, a frequency discriminator utilizes the in-phase and quadrature signals to initially coarse control the controllable oscillator frequency. The frequency shifting signals may be obtained from the controllable oscillator feeding phase shifting circuits, or they may be obtained from a combined circuit including a fixed oscillator with phase shifting circuits together with the controllable oscillator and appropriate mixing circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.