Non-volatile semiconductor memory device

US4385308A · kind A · utility

Assignee

• Tokyo Shibaura Denki Kabushiki Kaisha · JP

Inventor

• Yukimasa Uchida · Yokohama, JP

Key dates

• Filing date: May 20, 1980
• Grant date: May 24, 1983
• Expiry date: May 20, 2000

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/60

Abstract

A silicon nitride layer and a memory gate electrode are successively formed over a portion of a principal surface of a semiconductor substrate between drain and source regions formed therein and adjacent to the drain region via a thin silicon dioxide layer. A portion of the substrate principal surface, to which the source region is contiguous, is covered by a thick silicon dioxide layer, and a selection gate electrode is buried in the thick silicon dioxide layer. This two-input gate transistor construction constitutes a memory cell.