Planar chip-level power combiner
US4386324A · kind A · utility
11Cited by
3References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 5, 1980 |
| Grant date | May 31, 1983 |
| Priority date | — |
| Expiry date | Dec 5, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49175
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A chip-level power combiner comprises plural amplifier devices, a power divider, and a power combiner. The power divider and the power combiner are disposed in mirror-image fashion. Each divider/combiner comprises a first divider/combiner section having plural branch transmission lines cascading from/to a main transmission line, and a second divider/combiner section having plural feeder transmission lines cascading from/to each branch of the transmission line. Each of the branch and feeder transmission lines has an isolation resistor interposed between adjacent lines, and the feeder transmission lines are tapered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.