Dynamic semiconductor memory device with decreased clocks
US4387448A · kind A · utility
8Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1981 |
| Grant date | Jun 7, 1983 |
| Priority date | — |
| Expiry date | Apr 15, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a dynamic semiconductor memory device with decreased clocks having a pull up circuit associated with a pair of bit lines. The pull up circuit comprises a pair of first switching transistors connected between a power supply line and the associated bit line, and, a pair of second switching transistors. Each gate of the second switching transistors is connected to the bit line of opposite side. The turning on or off of the second switching transistor controls the gate potential of the first switching transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.