Loss-of-phase-lock indicator circuit
US4388598A · kind A · utility
7Cited by
8References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 3, 1980 |
| Grant date | Jun 14, 1983 |
| Priority date | — |
| Expiry date | Nov 3, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A loss-of-phase-lock indicator circuit is described which detects an out-limit voltage, whether steady or transitory. A pair of comparators, one for the high limit and the other for the low limit, are inserted in series between the tuning voltage and the sweep feedback amplifier, and are dc-coupled to the peak detector in the failure circuit. Additionally, a "dither" voltage is added in series with the phase detector, which ac voltage is large enough to swing the tuning voltage between limits at the loop amplifier output, but small enough to produce little effect on the output during phase lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.