Signal limiting integrated circuit
US4388632A · kind A · utility
3Cited by
4References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 3, 1980 |
| Grant date | Jun 14, 1983 |
| Priority date | — |
| Expiry date | Oct 3, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/761
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A simple silicon integrated circuit consists of two identical Schottky diodes formed in epitaxial pockets that are defined by P-N junction isolation walls. Metallization is provided to connect the diodes back-to-back in parallel and to provide terminal pads at the two nodes of the parallel circuit. Another metal film makes contact with the isolation wall and has an enlarged termination pad portion. This component may be connected across the input of an A/D converter to limit input signals to a small value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.