Hardware memory write lock circuit
US4388695A · kind A · utility
29Cited by
2References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 21, 1980 |
| Grant date | Jun 14, 1983 |
| Priority date | — |
| Expiry date | Feb 21, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware circuit for protecting against the accidental writing in an area of memory which contains critical data. In order to access the critical data memory area during a write cycle, it is necessary first to control predetermined memory access cycles which include, for example, the writing of predetermined data at a predetermined address. After detection of such a "fictitious" write cycle, the hardware allows the next write cycle to access the critical data memory area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.