Method of planarizing silicon dioxide in semiconductor devices
US4389281A · kind A · utility
23Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1980 |
| Grant date | Jun 21, 1983 |
| Priority date | — |
| Expiry date | Dec 16, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for planarizing a non-uniform thickness of oxide, for example silicon dioxide as is formed over oxide-filled trenches used in deep dielectric isolation in integrated circuits. The oxide is removed by a planarizing resist-etching process so that etching in thicker resist areas proceeds at a rate slower than etching in thinner resist areas. A referred etchant is HF gas and etching is preferably at an elevated temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.