Sample and hold circuit
US4389579A · kind A · utility
107Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1981 |
| Grant date | Jun 21, 1983 |
| Priority date | — |
| Expiry date | Feb 27, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit for producing an output voltage the magnitude of which is representative of the peak magnitude of a sampled input signal. The sample and hold circuit comprises a unity gain amplifier having an input terminal to receive said input signal and a cascoded output section for sourcing current at an output terminal. A discharge circuit is provided which includes a cascoded section for sinking current at said output terminal. Each of said cascoded sections being coupled to a capacitive load for charging or discharging the capacitor respectively to provide said output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.