Method for controlling the clock phase of a receiving system for digital data, phase recovery circuit for effectuating this method and digital data receiving system comprising said circuit
US4389727A · kind A · utility
9Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1981 |
| Grant date | Jun 21, 1983 |
| Priority date | — |
| Expiry date | Feb 23, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Method for controlling the phase of a decision circuit clock of a receiving system for digital data, according to which the frequencies above 1/T (T=data symbol period) are substantially eliminated, whereafter the phase deviation to be corrected is evaluated and the clock is shifted in accordance with this phase deviation, inclusive of its sign. An example of a circuit for using this method includes a lowpass filter circuit and an evaluation and phase shifting circuit for fixing the optimum decision instants of the decision circuit provided at the output of an adaptive filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.