Circuit for reproducing a clock signal
US4390801A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1982 |
| Grant date | Jun 28, 1983 |
| Priority date | — |
| Expiry date | Jun 2, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1403
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit for reproducing a clock signal from digital signals reproduced from a recording medium makes self-clocking possible. The circuit includes a phase lock loop having a voltage-controlled oscillator that generates an oscillation output at a frequency which is approximately equal to or an integral multiple of the frequency of the clock signal contained in the reproduced signal. A pulse generating device outputs pulses of a fixed amplitude, triggered by the leading or trailing edge of the input signal, to the phase lock loop. An oscillation device outputs pulses having approximately the same period as the clock signal period. The oscillation device is triggered by the leading or trailing edge of the input signal. A selecting device gates the output pulses of the oscillation device to the phase lock loop. The selecting device interpolates the output pulse spacing of the pulse generating device and the output pulses of the oscillation device so that a clock signal output is obtained from the phase lock loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.