Efficient means for implementing many-to-one multiplexing logic in CMOS/SOS
US4390988A · kind A · utility
21Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1981 |
| Grant date | Jun 28, 1983 |
| Priority date | — |
| Expiry date | Jul 14, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for multiplexing a plurality of input signals to a single output signal through the use of N and P channel FETs whereby complementary switching circuitry results in a minimization of power usage in either the active or static circuit conditions. This is accomplished by using a feedback technique and area sizing of the FETs to obtain optimum operational results in addition to the minimal power requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.