Cached multiprocessor system with pipeline timing
US4392200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1981 |
| Grant date | Jul 5, 1983 |
| Priority date | — |
| Expiry date | Feb 27, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor data processing system, the processors (30) and input/output devices (32) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), a memory management circuit (22) and an address translation circuit (24). The data processing system further includes random access memory (28) and a secondary storage facility (40, 42, 68, 70). The processors (30) and the input/output devices (32) use the memory management circuit (22), the address translation circuit (24) and the cache memory (20) in an ordered pipelined sequence. When a read command "misses" the cache memory (20), the CCU accesses the memory modules (28) for allocating its cache memory (20) and for returning read data to the processors (30) or input/output devices (32). The CCU also includes a duplicate tag store (67) that maintains a copy of the cache memory address tag store (20A) thereby to enable the CCU to update its cache memory when data is written into a memory location that is to be maintained in the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.