Semiconductor memory device technical field
US4392211A · kind A · utility
16Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1981 |
| Grant date | Jul 5, 1983 |
| Priority date | — |
| Expiry date | Feb 20, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device wherein a redundancy memory cell array incorporated with main memory cell matrixes is disclosed. Memory cells of the main memory cell matrixes are selected by first and third decoders while memory cells of the redundancy memory cell array are selected by second and third decoders. When the redundancy memory cell array is selected by the second decoder, the transmission of a clock signal to the first decoders is stopped by a switching circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.