Integrated circuit device connection process
US4392298A · kind A · utility
14Cited by
8References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1981 |
| Grant date | Jul 12, 1983 |
| Priority date | — |
| Expiry date | Jul 27, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming electrical interconnections in an integrated circuit which involves forming an insulating layer on the silicon chip on the lower of two conductive layers to be interconnected, opening a window in the insulating layer, filling the window with a metallic plug by a lift-off technique, and then forming an interconnection pattern extending over the layer and contacting the plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.