Communications subsystem having a self-latching data monitor and storage device
US4393461A · kind A · utility
13Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1980 |
| Grant date | Jul 12, 1983 |
| Priority date | — |
| Expiry date | Oct 6, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communications subsystem having a microprocessor coupled to an address bus and a data bus includes a latching register also coupled to the address bus and the data bus. The latching register is responsive to signals from the data bus and address bus for storing bits representative of a direct connect mode, a clear to send mode, and a bit oriented or byte control protocol mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.