Decoding and selection circuit for a monolithic memory
US4394752A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 1981 |
| Grant date | Jul 19, 1983 |
| Priority date | — |
| Expiry date | Jun 22, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.