Multiprocessor system with switchable address space
US4396978A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1980 |
| Grant date | Aug 2, 1983 |
| Priority date | — |
| Expiry date | Feb 13, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system comprising at least two microcomputers, one microcomputer (1) serves as a master to control the or each other microcomputer (2, 3 respectively) as a slave. In order to improve that utilization of the system the bus (4) of the master serves as a common bus and each slave has associated with it a buffer memory (5, 6 respectively) for the intermediate storage and transmission of data. The buffer memory can be connected, by means of an associated switching device (7, 8 respectively), alternately to the bus (9, 10, respectively) of the slave and to the common bus thereby switching the address field constituted by the buffer memory into the address space of the slave and into the address space of the master respectively. Furthermore, each slave has associated with it two interconnected input/output interfaces (11, 12 and 13, 14 respectively which serve for transmission of status signals concerning the master of the relevant slave. One of said interfaces is connected to the common bus, while the other interface is connected to the bus of the relevant slave. Each switching device is controlled by the corresponding input/output interface connected to the common b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.