Arbiter circuit
US4398105A · kind A · utility
21Cited by
6References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1981 |
| Grant date | Aug 9, 1983 |
| Priority date | — |
| Expiry date | Jan 22, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arbiter circuit includes a latch made of two crosscoupled NAND gates, one of which is a Schmitt NAND gate, a difference detector, and two output NOR gates. The output of the latch is coupled to the difference detector and to one input of the NOR gates. The NOR gates receive another input from the difference detector. The difference detector is responsive to a voltage difference that exceeds one V.sub.BE, thereby blocking signals that originate in the latch during oscillating or metastable states of the latch, which may include rut pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.