Multiple clock switching circuit
US4398155A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1981 |
| Grant date | Aug 9, 1983 |
| Priority date | — |
| Expiry date | Jun 15, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for switching between multiple asynchronous clocks is provided. A synchronizer comprising D-type flip-flops, which are controlled by a clock change signal, are provided for each control signal being switched. Output signals provided by the synchronizers are used to control MOS transistor gates which switch the asynchronous clocks to the circuit output. The synchronizers also control a clamping transistor gate which clamps the circuit output to a reference during a switching operation. An additional synchronizer provides synchronization between the clock change signal and the circuit output allowing the circuit output to be interrupted at a known state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.