Keyboard and display interface adapter architecture
US4398265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1980 |
| Grant date | Aug 9, 1983 |
| Priority date | — |
| Expiry date | Sep 15, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A unique interface adapter is coupled to a microprocessor by a three-wire self-clocking serial data bus for accommodating a twenty-key keyboard and an eight-digit display. The interface adapter includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from the data signal transmitted on two forward signal lines of the serial data bus. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether a control register or display register is to be loaded in response to the read/write signal with the data portion of the data signal. The control register signals activate four status indicating LED's, apply power to the display, select between a ten or sixteen digit display, enable an audio tone generator and reset a status bit flip-flop. The display register receives two BCD digits which are stored in a display memory. The keys of the keyboard are scanned at the same ti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.