Fabrication method for high power MOS device
US4398339A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1981 |
| Grant date | Aug 16, 1983 |
| Priority date | — |
| Expiry date | Sep 9, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V groov
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.