Instruction address stack in the data memory of an instruction-pipelined processor
US4399507A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1981 |
| Grant date | Aug 16, 1983 |
| Priority date | — |
| Expiry date | Jun 30, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4486
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction pipeline for a data processor is disclosed, in which instruction execution is carried out in a sequence of phases which include fetching the instruction from an instruction storage, computing a data storage address from the fetched instruction, accessing the data storage at the computed address to obtain a datum operand, and then carrying out the logical or arithmetic operation on the accessed datum in accordance with the fetched instruction. Branch and stack instructions and return instructions are accommodated by providing a return address stack in the data storage, which stores the next instruction store address to be returned to after a return operation has been completed. Since the instruction address stack in the data storage cannot be directly accessed by the instruction fetching stage of the pipeline until several instruction execution phases have transpired, without degrading the performance of the pipeline, a stack register is provided in the instruction fetch stage of the pipeline which contains a duplicate of the instruction store address presently residing at the top of the instruction address stack. Then when a return instruction is encountered in the i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.