Non-volatile, electrically erasable and reprogrammable memory element
US4399523A · kind A · utility
24Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1980 |
| Grant date | Aug 16, 1983 |
| Priority date | — |
| Expiry date | Aug 22, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/686
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to non-volatile electrically erasable and reprogrammable memories produced by CMOS technology. According to the invention, each memory element comprises only a single p-channel transistor having a polycrystalline silicon floating gate capacitively coupled to a control electrode. The thicknesses of injection oxide and gate oxide are such that the element can be programmed by avalanche of the drain-substrate junction and erased by field emission of electrons from the floating gate towards the substrate. All the voltages required can be generated on the circuit of the memory from a battery voltage of 1.5 volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.