Level detection circuit
US4400633A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 1980 |
| Grant date | Aug 23, 1983 |
| Priority date | — |
| Expiry date | Oct 2, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/04
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A level detection circuit comprises a peak value detection and holding circuit having a capacitor which detects and holds the peak value of an input signal by charging the capacitor, an operation control circuit for supplying the input signal to the maximum value detection and holding circuit during a specific time interval to perform maximum value detection and holding operation, a discharge circuit which performs constant current discharge of a charged electric charge in the capacitor of the maximum value detection and holding circuit after the specific time interval, and a detection circuit for detecting the level of the input signal by measuring the time interval between a time point the constant current discharge of the capacitor by the discharge circuit is initiated and a time point the terminal voltage of the capacitor reaches a specific voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.