Resonant scan deflection circuit with flyback voltage limiting
US4400653A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 1982 |
| Grant date | Aug 23, 1983 |
| Priority date | — |
| Expiry date | Mar 24, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention is designed to protect a resonant scan deflection transistor in a deflection circuit from extremely high flyback voltage pulses. The deflection transistor is protected against high flyback voltage pulses even though: the B+ voltage on the deflection circuit varies over a wide range, the rate of the base drive signal varies over a wide range, and the turn-off delay time of the deflection transistor varies from device to device and for any one device as the base drive signal rate changes. The circuit of this invention compensates for the variations in turn-off delay time (t.sub.D) of the deflection transistor at different horizontal scanning rates, and, in response to this compensation, compares the B+ voltage level with the current in the deflection coil. An extra turn-off trigger signal is developed in response thereto for energizing the deflection transistor drive circuit. In response to the trigger signal, the deflection transistor turns off. Since the extra trigger signal (if needed) is received before the sync pulse is received, the deflection transistor turns off and is thereby protected against a dangerously large flyback voltage pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.