Data processor control subsystem
US4400776A · kind A · utility
1Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1980 |
| Grant date | Aug 23, 1983 |
| Priority date | — |
| Expiry date | Sep 12, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved data processor control subsystem in which a cycle counter having a plurality of cascade-connected stages also comprises one or more supplemental or dummy stages, which can be selectively inserted or removed from the chain of cascade-connected stages, to alter the number of sub-cycles in an operating cycle, thereby decreasing the complexity of associated decoding circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.