Digital sample and hold circuit
US4401974A · kind A · utility
7Cited by
4References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1979 |
| Grant date | Aug 30, 1983 |
| Priority date | — |
| Expiry date | Feb 12, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit for an automotive speed control system is disclosed which includes a non-monotonic digital-to-analog converter suitable for fabrication as a highly dense monolithic circuit. The non-monotonic digital-to-analog converter precludes the occurrence of large positive errors in the analog output value, which might be caused by tolerance errors in the ratio of binary-weighted currents within the digital-to-analog converter, by including offsetting negative errors within the design of the digital-to-analog converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.