Radiation hardened-self aligned CMOS and method of fabrication
US4402002A · kind A · utility
2Cited by
12References
4Claims
0Family size
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Key dates
| Filing date | Sep 25, 1980 |
| Grant date | Aug 30, 1983 |
| Priority date | — |
| Expiry date | Sep 25, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
Abstract
A radiation hardened CMOS formed by applying a radiation hard gate oxide layer on a silicon substrate, applying silicon doped aluminum gates on the gate oxide, and by ion implanting and annealing source and drain regions using said gates as masks at a temperature of or below 500 degrees centigrade. Using an N.sup.- type substrate, a P.sup.+ guard ring is formed at the interface of the P.sup.- well of the N channel MOS device and the N.sup.- substrate before the formation of the gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.