Plural storage areas with different priorities in a processor system separated by processor controlled logic
US4402041A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1980 |
| Grant date | Aug 30, 1983 |
| Priority date | — |
| Expiry date | Oct 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed apparatus for keeping two or more distinct groups of data separate from each other within a processor based system. The system employs at least two system areas, where one system area is assigned to have higher priority data than the other. By detecting the priority of a data operation, the lower priority system area is prevented by means of gates from having high priority data written into the lower priority system area. The higher priority system area can read data from the lower priority system area at all times and the lower priority system area can write data into the higher priority system area at all times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.