Semiconductor memory circuit
US4402066A · kind A · utility
4Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1981 |
| Grant date | Aug 30, 1983 |
| Priority date | — |
| Expiry date | Feb 17, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory circuit having reduced read-access time and comprising a plurality of first and second common line pairs, each including a bit line and a data line connected in series is disclosed. Conventional static RAM memory cells are connected between each of the bit line pairs. A write-control circuit and sense amplifier are connected between each of the data bus pairs. At least one bypassing transistor is connected between each of the first and second common line pairs for conducting current between each of the lines of the common line pairs, thus reducing the read-access time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.