Delay correction circuit
US4402079A · kind A · utility
9Cited by
3References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1980 |
| Grant date | Aug 30, 1983 |
| Priority date | — |
| Expiry date | Oct 24, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/05
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A delay correction circuit is described for use with an elastic store in a PCM time division multiplexed system. The relative position of the read and write addresses supplied to the elastic store are monitored. In the event that either the read or write addresses are overtaking the other and are within a predetermined range of addresses, either the read or write address source will be initialized at a predetermined time such that the read and write addresses have new relative position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.