Method for manufacturing a semiconductor integrated circuit utilizing polycrystalline silicon deposition, oxidation and etching
US4404737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1980 |
| Grant date | Sep 20, 1983 |
| Priority date | — |
| Expiry date | Nov 28, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor integrated circuit includes diffusing an impurity of a second conductivity type into polycrystalline silicon layers formed on a first conductivity region in a substrate to form second conductivity regions, the polycrystalline silicon layers constituting first electrode wirings to the second conductivity regions; forming a thick oxidation film on the polycrystalline silicon layers and a thin oxidation film on the exposed surface of the substrate by a heat oxidation treatment; and removing the thin oxidation film to form a second electrode wiring to the first conductivity region, said second electrode wiring being insulated from the polycrystalline silicon layers by the thick oxidation film. The method provides integrated circuits such as I.sup.2 L circuits which are capable of high speed operation and a high packaging density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.