Method of fabricating an I.sup.2 L element and a linear transistor on one chip
US4404738A · kind A · utility
13Cited by
11References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1981 |
| Grant date | Sep 20, 1983 |
| Priority date | — |
| Expiry date | Sep 25, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/658
Abstract
An integrated circuit device is provided in which an I.sup.2 L element and linear transistor are formed on a single chip such that they coexist. In this device, the base and collector regions of a vertical transistor of the I.sup.2 L element are formed such that they are deeper than the base and emitter regions of the linear transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.