Data processing system having apparatus in a communications subsystem for establishing byte synchronization
US4405979A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1980 |
| Grant date | Sep 20, 1983 |
| Priority date | — |
| Expiry date | Oct 6, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing system having a communications subsystem operating in a byte control protocol mode includes apparatus for establishing byte synchronization between the data circuit terminating equipment (DCE) and the communications subsystem. The apparatus includes a flop for receiving a stream of predetermined binary bits, a counter generating count signals indicative of the number of binary bits between a byte timing signal from the DCE and the last binary ONE bit of the last byte containing all binary ONE bits, a shift register for the serial shifting of the transmitted data bits and a multiplexer responsive to the count signals for selecting the shift register terminal, thereby timing the byte timing signal to the binary bit stream of data bits, including bytes of all binary ONE bits and a byte of all binary ZERO bits, followed by bytes of data bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.