N-Channel JFET device having a buried channel region, and method for making same
US4407005A · kind A · utility
4Cited by
2References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1981 |
| Grant date | Sep 27, 1983 |
| Priority date | — |
| Expiry date | Oct 5, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface of the body outside the p-well. A buried channel connects the source and drain. A p-layer above the buried channel forms the top gate. Gate leakage current and noise are very low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.