Process and structure for minimizing delamination in the fabrication of multi-layer ceramic substrate
US4407007A · kind A · utility
38Cited by
3References
3Claims
0Family size
Assignee
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Key dates
| Filing date | May 28, 1981 |
| Grant date | Sep 27, 1983 |
| Priority date | — |
| Expiry date | May 28, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4641
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process and a solid plane structure for minimizing delamination during sintering in the fabrication of multi-layer ceramic substrates, wherein the solid plane structure is designed to obtain maximum ceramic to ceramic interface contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.