MOS Device including a substrate bias generating circuit
US4409496A · kind A · utility
14Cited by
5References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 28, 1981 |
| Grant date | Oct 11, 1983 |
| Priority date | — |
| Expiry date | Jan 28, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An MOS device including a substrate bias generating circuit, comprising: a clock generator for receiving an external clock signal and generating first and second internal clock signals; an internal circuit operated by the first and second internal clock signals; a pumping circuit driver for generating third and fourth internal clock signals in synchronization with the first and second internal clock signals and; a pumping circuit operated by the third and fourth internal clock signals. In this device, when the substrate potential (V.sub.BB) is relatively high, currents flow from the substrate to the pumping circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.