Power-on reset circuit
US4409501A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1981 |
| Grant date | Oct 11, 1983 |
| Priority date | — |
| Expiry date | Jul 20, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-on reset circuit in which a first CMOS inverter drives a second CMOS inverter to turn on a third and fourth CMOS inverter. A reset pulse results at the output of the fourth inverter while the third inverter holds a first MOSFET in an off condition and a capacitor is charged through a resistive network comprised of two MOSFETs. When the capacitor is charged past the switching point of the first inverter, the POR pulse is terminated and the first MOSFET is turned on, allowing the capacitor to be charged to the point that no static current flows through the reset circuit because no static current flows through the first inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.